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| INDEX PRELIMINARY MX23L6430 64M-Bit Synchronous Mask ROM FEATURES * Switchable organization : 4M x 16 ( word mode ) or 2M x 32 ( double word mode ) * Power supply 3.0V ~ 3.6V * TTL compatible with multiplexed address * All inputs are sampled at rising edge of system clock * Read performance : - 4-1-1-1@33MHz(RAS Latency=1, CAS Latency=3 ) - 5-1-1-1@50MHz(RAS Latency=1, CAS Latency=4 ) - 7-1-1-1@66MHz(RAS Latency=2, CAS Latency=5 ) - 7-1-1-1@100MHz(RAS Latency=2, CAS Latency=5) - Clock to valid output delay (tSAC) : 6ns(Max.) * MRS cycle with address key programs : - RAS Latency : 1 & 2 - CAS Latency : 2 ~ 8 - Burst Length : 8 double word - Burst Type : Sequential or Interleaved * DQM for data-out masking * Package : 86 pin TSOP(II) GENERAL DESCRIPTION The 64M synch. MROM is a synchronous high bandwidth mask programmable ROM with MXIC's high performance CMOS process technology and is organized either as 4M x 16 bits or 2M x 32 bits depending on polarity of WORD pin. Synchronous design allows precise cycle control , with the use of system clock, I/O transaction are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system application. PIN CONFIGURATION VCC Q0 VCCQ Q16 Q1 VSSQ Q17 Q2 VCCQ Q18 Q3 VSSQ Q19 MR VCC DQM NC CAS RAS CS WORD A12 A11 A10 A0 A1 A2 NC VCC NC Q4 VSSQ Q20 Q5 VCCQ Q21 Q6 VSSQ Q22 Q7 VCCQ Q23 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS Q31 VSSQ Q15 Q30 VCCQ Q14 Q29 VSSQ Q13 Q28 VCCQ Q12 NC VSS NC NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 NC VSS NC Q27 VCCQ Q11 Q26 VSSQ Q10 Q25 VCCQ Q9 Q24 VSSQ Q8 VSS MX23L6430 P/N:PM0575 REV. 1.1, FEB. 09, 1999 1 INDEX MX23L6430 BLOCK DIAGRAM Row Decoder RA12-0 64M bits cell array Q0 : : Q31 Sense AMP. Output Bufer Row Buffer Address Register ADD LRAS CA7-3 Column Decoder CF2.0 CA2-0 LCAS Mode Register MRE LOE Col. Buffer CKEB Timing Register CLK CKE MR RAS CAS CS DQM WORD PIN DESCRIPTION Symbol CLK CS CKE A0 ~ A12 Function Active on the rising edge to sample all inputs Disable or enable device operation by masking or enabling all inputs except CLK and CKE Clock Enable Mask system clock to freeze operation from next clock cycle and disable input buffers for power down in standby. Address Row/Column addresses are multiplexed on the same pins. Row address : RA0~RA12 , Col. address : CA0~CA7(x32) or CA0~CA8(x16) Row address Strobe Latch row addresses on the rising edge of the CLK with RAS low and enable row access Column address Strobe Latch column addresses on the rising edge of the CLK with CAS low and enable column access Mode Register Set Enable mode register set with MR low (simultaneously CS , RAS and CAS are low) Data Output Data output according to the rising edge of CLK Power Supply / Ground Power and ground for the input buffers and the core logic Data Output Power/ Ground Power and ground for the output buffers to provide improved noise immunity x32/x16 Mode Selection Double word mode / word mode, depending on polarity of WORD pin. Should be set before CAS enabling Data Out Masking It works similar to OE during read operation No Connection REV. 1.1, FEB. 09, 1999 Name System Clock Chip Select RAS CAS MR Q0 ~ Q31 VDD/VSS VDDQ/VSSQ WORD DQM NC P/N:PM0575 2 INDEX MX23L6430 ABSOLUTE MAXIMUM RATINGS Item Power Supply Voltage Input Voltage Output Voltage Ambient Operating Temperature Storage Temperature Symbol VCC VI VO Topr Tstg Ratings -0.5V to 4.6V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V 0 to 70C C -55C to 125 C DC CHARACTERISTIC (Ta=0C~70C, VCC=3.3V0.3V) Item Standby Current Active standby Current Burst Operating Current Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Symbol ICC3P ICC3PS ICC3N ICC4 IIL IOL VIH VIL VOH VOL MIN. -10uA -10uA 2.0V -0.3V 2.4V MAX. 1mA 100uA 50mA 150mA 10uA 10uA VDD+0.3V 0.8V 0.4V Conditions CKE=VIL, tCC=Min. CKE=0, tCC=Min. CS=VIH, tCC=Min., All outputs open (Note 1) tCC=Min., All outputs open 0 Note 1: The active standby current is also for clock suspend mode. P/N:PM0575 REV. 1.1, FEB. 09, 1999 3 INDEX MX23L6430 AC CHARACTERISTIC (Ta=0 C~70 VCC=3.3V0.3V) C, Symbol up to 100MHz MIN. MAX. CLK Cycle Time tCC 10ns CLK to Valid Output Delay tSAC 6ns Data Output Hold Time tOH 4ns CLK High Pulse Width tCH 3ns CLK Low Pulse Width tCL 3ns Input Setup Time tSS 4ns Input Hold Time tSH 2ns CLK to Output in Low-Z tSLZ 0ns CLK to Output in High-Z tSHZ 6ns Power Down Exit Setup Time tPDE tSS+tCCRow Active to Row Active tRC 6 cycles CAS Enable to Row Active tCR 4 cycles Valid CAS Enable to tCCD 4 cycles Valid CAS Enable Item up to 66MHz MIN. MAX. 15ns 6ns 4ns 4ns 4ns 4ns 2ns 0ns 10ns tSS+tCC 6 cycles 4 cycles 4 cycles up to 50MHz MIN. MAX. 20ns 6ns 4ns 6.5ns 6.5ns 4ns 2ns 0ns 15ns tSS+tCC 4 cycles 3 cycles 3 cycles up to 33MHz MIN. MAX. 30ns 6ns 4ns 11.5ns 11.5ns 4ns 2ns 0ns 25ns tSS+tCC 4 cycles - (Note 1) 3 cycles - (Note 2) 3 cycles - (Note 2) Note 1: (RAS latency+CAS latency)@33MHz, (RAS latency+CAS latency-1)@50MHz, 66MHz,100MHz Note 2: Equal to (CAS latency)@33MHz, (CAS latency-1)@50MHz, 66MHz, 100MHz AC TEST CONDITION Input Pulse levels Input and Output Timing Levels Input Rise and Fall Times Output Load VIH/VIL=2.4V/0.4V 1.4V tR/tF=1ns/1ns LVTTL *Note: If CLK transition time is longer than 1ns, timing parameters should be compensated. Add (tR+tF)/2-1ns for transition time longer than 1ns. Transitions time is measured between VIL(Max.) and VIH(Min.) P/N:PM0575 REV. 1.1, FEB. 09, 1999 4 INDEX MX23L6430 *LVTTL: 1.4V 3.3V 50 ohms 1200 ohms Output 850 ohms 50pF Output Z0=50 ohms 50pF (1) DC Output Load Circuit (2) AC Output Load Circuit CAPACITANCE PARAMETER Input Capacitance Output capacitance SYMBOL Cin Cout MIN. MAX. 5 7 UNIT pF pF P/N:PM0575 REV. 1.1, FEB. 09, 1999 5 INDEX MX23L6430 FUNCTION TRUTH TABLE (V=valid, X=don't care, H=Logic High, L=Logic Low) COMMAND Register Row Active Read Burst Stop Precharge on DRAM Power Down & Clock Suspend DQM No Operation Standby Entry Standby Exit Mode Register Set Row Access & Latch Col. Access & Latch CKEn-1 H H H H H H L H H H H H Organization Control H H CKEn x x x x x L H x x x x x x x CS L L L L L x x x H L L L L L RAS CAS L L H H L x x x x H H L H H L H L H H x x x x H L L L L MR L H H L L x x x x H L H H H DQM x x x x x x x V x x x x x x Add. Code RA CA x x x x x x x x x CA CA WORD NOTES x x x x x x x x x x x x H L 3 4 4 4 4 5 5 2 1 Notes : 1. A0~A6 : Program keys. After power up, mode register set should be set before entering other input command, After the mode register set command is completed, no new commands can be issued for 3 CLK cycles, and MR state must be defined "H" within 3 CLK cycles. 2. In the case CKE is low, two standby modes are possible. Those are standby mode in power-down and active standby mode in clock suspend. Power Down : CKE=L ( at all parts except the range of sensing and data out operation ) Clock Suspend : CKE=L ( at the range of sensing and data out operation) 3. DQM sampled at rising edge of a CLK makes a Hi-Z state or data output state, delayed by 2 CLK cycles. 4. NOP(No Operation) state on syn. MROM includes not only NOP but also precharge, refresh and write state on syn. DRAM . 5. Organization mode selection control is decided simutaneously with column access start, and according to the polarity of WORD pin. P/N:PM0575 REV. 1.1, FEB. 09, 1999 6 INDEX MX23L6430 MODE REGISTER FIELD TABLE (programmed with MRS) RAS Latency A6 Length 0 1 1 2 CAS Latency A5 A4 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 A3 0 1 0 1 0 1 0 1 Length reserved 2 3 4 5 6 7 8 Burst Type A2 Type 0 sequential 1 interleave Burst Length A1 A0 0 0 0 1 1 0 1 1 Length reserved 4 8 reserved Notes : 1. After power up, mode register set should be completed at one time and fixed to "H" within 3 CLK cycles. 2. After power up, when user wants to change mode register, user must exit from power down mode and start mode register set before entering normal operation mode . 3. The power-up default mode register field : RAS latency -> 2, CAS latency ->5, Burst type -> sequential, Burst length -> 4 4. The default mode register field is ROM Code changeable. BURST SEQUENCE Burst Length = 4 (x32) Initial Col. Addr. CA1 CA0 0 0 0 1 1 0 1 1 Burst Length = 8 (x32) Initial Col. Addr. CA2 CA1 CA0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Sequential (R)(R) 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 0 Interleave (R)(R) 0 1 2 1 0 3 2 3 0 3 2 1 4 5 6 5 4 7 6 7 4 7 6 5 Sequential (R)(R) 0 1 1 2 2 3 3 0 Interleave (R)(R) 0 1 1 0 2 3 3 2 2 3 0 1 3 0 1 2 2 3 0 1 3 2 1 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 P/N:PM0575 REV. 1.1, FEB. 09, 1999 7 INDEX MX23L6430 DEVICE OPERATION CLOCK (CLK) The clock input (CLK) is used as the reference for SMROM synchronous operation with square wave signal applied externally at cycle time tCC. All operations are synchronized to the rising edge of the clock. The clock transition must be monotonic between VIL and VIH . During operation with CKE high, all inputs are assumed to be in valid state for the duration of set-up and hold time around positive edge of the clock. CLOCK ENABLE (CKE) The clock enable (CKE) gates the clock into the SMROM and is asserted high during all cycles, except power down, and clock suspend mode. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled tPDE prior to valid command. In power down or clock suspend mode, if the CKE goes low synchronously with clock ( set-up and hold time ), the internal clock is suspended from the next clock eycle. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "tPDE" before the positive edge of CLK, the chip becomes active from the same clock edge to accept all the input commands. NOP (No Operation) When RAS, CAS and MR are high, the SMROM performs no operation (NOP) and does not initiate any new command. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR and all the address inputs are ignored. NOP of SMROM inclides precharge, refresh, and write state of SDRAM. In addition, when mode register set command is entered in the middle of normal operation, for SMROM, it's an illegal state . MODE REGISTER SET (MR) The mode register stores the data for controlling the various operating modes of SMROM including RAS latency, CAS latency, burst type and burst length. The default value of the mode register can be defined by ROM code option. The mode register is programmed by asserting low on CS, RAS, CAS, and MR and the states of the address pins A0 ~ A6 is the data written in the mode register. After mode register set command is completed, no new command can be issued for 3 clocks cycles. WORD MODE SELECTION CONTROL Mode selection control is decided simutaneously with column access according to WORD pin voltage level, high level for double word mode ( X32 ) and low level for word mode ( X16 ). ADDRESS DECODING The address pins are latched by externally applying two commands. The first command, RAS asserted low, latches the row address into the device. A second command, CAS asserted low, subsequently latches the column address . DQM OPERATION The DQM is used to mask output operation and works similar to OE. The DQM masking occurs two cycles later in the read cycle, and operates synchronously with clock. LATENCY There is latency between when a read command is given and when data is available on the I/O buffers. The RAS to CAS delay is defined as the RAS latency, and the CAS to data delay is the CAS latency. BURST READ The burst read command is used to access burst of data on consecutive clock cycles from an active row state. The burst read command is issued by asserting low on CS and CAS with RAS and MR high on the positive edge of the clock, after RAS latency number of clock cycles from row active command .The first output appears in CAS latency number of clock cycles after the issue of burst read command. The output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep data gapless. The burst stop command is valid during burst data out or between read command and data out. The data bus go to Hi-Z after the CAS latency from the burst stop command is satisfied. The burst stop command is asserted CS, MR low and CAS, RAS high or the same state as pre-charge on SDRAM. The interval between read command ( column address presented ) and burst stop command is one cycle minimum .The interval between the burst stop command and the next row active command is also one cycle minimum. P/N:PM0575 REV. 1.1, FEB. 09, 1999 8 INDEX MX23L6430 POWER-UP The following power-up sequence is recommended : 1. Power must be applied to either CKE and DQM inputs to pull them high and the other pins are NOP condition at the inputs to pull them high and the other pins are NOP condition at the inputs before or along with VDD and VDDQ supply . 2. Preform a mode register set cycle to program the mode value or use the default value. 3. At the end of three clock cycles from the mode register set cycle, if mode register set is active , the device is ready for power-up, all outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence. READ CYCLE 1: Normal @RAS Latency=2, CAS Latency=5, 100MHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK tCC CKE VIH tCH tCL tSS CS tSH RAS CAS Addr RAa CAa RAb tSAC CAb tOH Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Data BL=4 tRC Data BL=8 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qb0 Qb1 Qb2 Qb3 Qb4 MR WORD Row Active Burst Read P/N:PM0575 REV. 1.1, FEB. 09, 1999 9 INDEX MX23L6430 READ CYCLE 2: Normal with complete data out in BL=8 @RAS Latency=2, CAS Latency=5, 100MHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK CKE VIH CS RAS CAS Addr RAa CAa RAb CAb Data BL=8 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 MR WORD P/N:PM0575 REV. 1.1, FEB. 09, 1999 10 INDEX MX23L6430 READ CYCLE 3: Consecutive Column Access @RAS Latency=2, CAS Latency=5, 100MHz 0 1 2 3 4 7 5 6 8 9 10 11 12 13 14 15 16 17 18 CLK CKE VIH CS RAS CAS Addr RAa CAa tCCD CAb CAc CAd Data BL=4 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Data BL=8 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 MR WORD P/N:PM0575 REV. 1.1, FEB. 09, 1999 11 INDEX MX23L6430 READ CYCLE 4: Consecutive Column Access with complete data out in BL=8 @RAS Latency=2, CAS Latency=5, 100MHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK CKE VIH CS RAS CAS Addr RAa CAa CAb Data BL=8 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 MR WORD P/N:PM0575 REV. 1.1, FEB. 09, 1999 12 INDEX MX23L6430 READ CYCLE 5: Consecutive Column Access to Normal Read @RAS Latency=2, CAS Latency=5, 100MHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK CKE VIH CS RAS CAS Addr RAa CAa CAb CAc tCR RAd CAd Data BL=4 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Data BL=8 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 MR WORD P/N:PM0575 REV. 1.1, FEB. 09, 1999 13 INDEX MX23L6430 READ CYCLE 6: Mode Register Set 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK CKE VIH CS RAS CAS Addr Code RAa Data Hi-Z MR MRS Row Active P/N:PM0575 REV. 1.1, FEB. 09, 1999 14 INDEX MX23L6430 READ CYCLE 7: Clock Suspend & Clock Suspend Exit @RAS Latency=2, CAS Latency=5, 100MHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK CKE Internal CLK CS RAS CAS Addr RAa CAa Data BL=8 Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 MR WORD Clock suspend Clock suspend exit P/N:PM0575 REV. 1.1, FEB. 09, 1999 15 INDEX MX23L6430 READ CYCLE 8: Power Down & Power Down Exit @RAS Latency=2, CAS Latency=5, 100MHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK CKE Internal CLK CS RAS CAS Addr RAa CAa Data Qa6 Qa7 Qa0 MR WORD power down power down exit row active P/N:PM0575 REV. 1.1, FEB. 09, 1999 16 INDEX MX23L6430 READ CYCLE 9: Burst Stop or Interrupted by Precharge Case 1) during burst read operation 0 1 2 3 4 5 6 7 8 9 10 Command RD PRE STOP data (CAS latency=2) Qa0 Qa1 data (CAS latency=3) data (CAS latency=4) Qa0 Qa1 Qa0 Qa1 data (CAS latency=5) Qa0 Qa1 Col Active P/N:PM0575 REV. 1.1, FEB. 09, 1999 17 INDEX MX23L6430 Case 2) between read command and data out 0 1 2 3 4 5 6 7 8 9 10 Command RD PRE STOP data (CAS latency=2) Qa0 data (CAS latency=3) data (CAS latency=4) Qa0 Qa0 data (CAS latency=5) Qa0 Col Active P/N:PM0575 REV. 1.1, FEB. 09, 1999 18 INDEX MX23L6430 READ CYCLE 10: Normal with data masking @ RAS Latency=2, CAS Latency=5, 100MHz 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CLK tCC tCH tCL CKE VIH tSS tSH CS RAS CAS Addr RAa CAa RAb CAb Data tSS Qa0 Qa3 Qb0 Qb1 Qb2 Qb3 DQM MR WORD Row Active Burst Read P/N:PM0575 REV. 1.1, FEB. 09, 1999 19 INDEX MX23L6430 REVISION HISTORY REVISION 1.1 DESCRIPTION To Add 100MHz Speed Grade PAGE P1,4 DATE Feb/09/1999 P/N:PM0575 REV. 1.1, FEB. 09, 1999 20 INDEX MX23L6430 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-8888 FAX:+886-3-578-8887 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 21 |
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